The invention relates to a comparator circuit. Comparators are used in order to map an input variable, for example an input voltage, onto a logic state. If the input voltage is below the threshold value of the comparator, then the output voltage from the comparator is at the first logic level, for example low (L), and if the input voltage is above the threshold value, then the output voltage is at the second logic level, for example high (H).
A quality criterion for comparators is the accuracy with which a specific, defined switching threshold is carried out. In a sensor system, or else in comparators, which are used in peripheral circuit parts, one problem, which often arises is that the input signal of the comparator is subject to interference or noise. This leads to the comparator switching backward and forward in a rapid sequence between the logic levels L and H. The signal bouncing is undesirable. Bouncing must be avoided, particularly when the aim, for example, is to count events or to generate a clock on the basis of an external signal.
One known remedial measure is to provide the comparator with hysteresis. In this case, the threshold above which the input signal must rise is higher for switching from L to H than for switching back from H to L. If the interval between the switching thresholds is made greater than the amplitude of the interference to be expected, then unambiguous signal evaluation is feasible. However, the interference immunity is gained at the expense of switching threshold accuracy, since it is split between two values. If the switching thresholds are chosen such that the upper and the lower value are each symmetrical with respect to the actually desired switching threshold, then this admittedly results in the minimum discrepancies overall, but there is now no longer any switching threshold precisely where it actually should be. This is irrelevant if one just wishes to count events. However, if accurate position or time determination is also intended to be carried out, for example in the sensor system, this response has a disturbing effect. For example, for sensors, which have to evaluate an approximately sinusoidal signal, for example gear wheel sensors, it is advantageous for reasons of accuracy to switch at the signal zero crossing, while one would have to switch in the vicinity of the signal peak, for interference immunity reasons.
It is accordingly an object of the invention to provide a comparator circuit that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which has an accurate, largely hysteresis-free switching threshold, but which also offers interference immunity, by which disturbing bouncing is avoided.
With the foregoing and other objects in view there is provided, in accordance with the invention, a comparator circuit. The comparator circuit contains an input for receiving an input signal, an output terminal outputting an output signal, and a first comparator connected to the input and receiving the input signal. When the input signal exceeds a threshold value T1, the first comparator generates a first output signal switching from a first logic signal to a second logic signal, in which case a switching of the output signal from the first logic signal to the second logic signal can be initiated only by the first comparator switching from the first logic signal to the second logic signal. A monitoring circuit is connected between the input and the output terminal. The monitoring circuit contains a second comparator connected to the input and has a switching hysteresis with a switching-on threshold T2 and a switching-off threshold T3, where T2 greater than T3. The second comparator and the first comparator each have an output. An output circuit and a logic circuit are provided. The logic circuit is connected to the output circuit, to the output of the first comparator, and to the output of the second comparator. The logic circuit links the output of the first comparator and the second comparator to the output circuit in such a manner that, when the input signal exceeds the threshold value T1, the output circuit emits the second logic signal and then remains inhibited against returning to the first logic signal until the input signal has once again fallen below the threshold value T1 after exceeding the switching-on threshold value T2. A reset circuit is connected to the output circuit and the logic circuit. The reset circuit is able to reset the output circuit to a quiescent state irrespective of a state of the first comparator and the second comparator, and in the quiescent state the output signal at the output terminal is at the first logic signal, and the output circuit maintains its present state until the first comparator and the second comparator output signals are the first logic signal.
According to the invention, the undesirable bouncing is avoided in that, after switching from the first to the second logic level, the circuit output remains inhibited against switching back until the input signal has reached a second threshold value, which is higher than the switching threshold of the first comparator. The switching threshold of the circuit output is governed by the switching threshold of the comparator, but the switching times are dependent on whether and when the input signal reaches the second threshold value.
According to one refinement of the invention, the monitoring circuit contains a further comparator, which has hysteresis and whose input is connected to the circuit input, and a logic circuit. The monitoring circuit is configured such that the comparator can emit a signal only when the input signal supplied to it is sufficiently large to switch the further comparator that has hysteresis, as well. If the input signal is too low, the output signal is not switched. Although the comparator does not act directly on the output itself, it must, however, enable the circuit to allow the comparator to switch back again and to produce a new output flank.
In one particularly advantageous refinement of the invention, a reset circuit is provided, by which the comparator circuit can be switched to a defined initial state, which is independent of the switching states of the comparators when the reset signal is present. The purpose of the reset circuit is that the very first switching (the very first output flank or edge) of the comparator is not defined by a reset event or by the reset end, but occurs precisely at the time at which the input signal would lead to switching of the comparator. The reset signal changes the output signal from the comparator circuit to the reset state, and locks the comparator output circuit. Enabling does not take place until the time when the internal comparator output matches the reset state, which is present at the output. This ensures that the next output flank at the output of the comparator circuit is also related to switching of the comparator.
A further advantage of the reset circuit is that a defined output situation is reached, in which, for example, the output signals from the comparators assume the level; this has an advantageous effect on the power consumption of the circuit.
In accordance with an added feature of the invention, the output circuit is a flip-flop with a set input, a reset input and an output being the output terminal.
In accordance with an additional feature of the invention, the logic circuit has a first AND gate, a second AND gate, a first NOT gate with an output, and a second NOT gate with an output. The first AND gate has a first input connected to the output of the first comparator and a second input connected to the output of the second NOT gate. The second NOT gate has an input connected to the output of the second comparator. The second AND gate has a first input connected to the output of the first NOT gate and a second input connected to the output of the second comparator. The first NOT gate has an input connected to the output of the first comparator.
In accordance with a further feature of the invention, the flip-flop includes a first NOR gate having an output and inputs and a second NOR gate having an output and inputs. The output of the first NOR gate is connected to one of the inputs of the second NOR gate, and the output of the second NOR gate connected to one of the inputs of the first NOR gate.
In accordance with another feature of the invention, the reset circuit includes a third NOT gate having an input and an output; an input connection connected to the input of the third NOT gate; and a third AND gate having a first input connected to the output of the second NOR gate of the flip-flop, a second input connected to the output of the third NOT gate, and an output connected to one of the inputs of the first NOR gate of the flip-flop. A further flip-flop is provided and has a set input, a reset input connected to the input connection for receiving a reset signal, and an output connected to a third input of the first AND gate and to a third input of the second AND gate. An exclusive-OR gate is provided and has an output connected to the set input of the further flip-flop, a first input connected to the output of the first NOT gate and to the second input of the second AND gate, and a second input connected to the output of the third AND gate.
In accordance with a further added feature of the invention, the threshold value T1, the switch-on threshold T2 and the switch-off threshold T3 are chosen such that T3 less than T1 less than T2.
In accordance with a concomitant feature of the invention, the first logic signal is low (logic 0), and the second logic signal is high (logic 1).
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a comparator circuit, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.